Current chip designs include large amounts of random access memory (RAM) and the trend is for increasing requirements for on-chip RAM (in the order of hundreds of kilobytes). Like any other logic, RAMs consume power, consisting of sense amp power, output driver power, clock power etc. When a RAM is not accessed for a read or write access operation, the RAM sense amps and drivers are typically turned off, but the RAM clock continues to toggle, leading to a certain amount of idle power dissipation.
Large logical RAMs are usually architected as an array of smaller RAM EBBs (Embedded Blocks), as shown in FIG. 1. FIG. 1 illustrates a conventional 256×1024 RAM having four banks of four EBBs 64×256 bits. RAM compilers typically have limitations that prevent the generation of a single large RAM EBB, so designers often resort to generating a number of smaller RAM EBBs, such as RAM EBBs 101(1)-101(16), which are organized as a single logical RAM 100. The RAM 100 is a 256×1024 bits RAM, organized as a group of sixteen 64×256 RAMs 101(1)-101(16). The logical RAM 100 is organized in four banks, bank1 102(1) thru bank4 102(4), 256×256 bits each. When a RAM bank, for example bank1 102(1), is accessed for a read or write access operation, all four RAM banks 102(1)-102(4) receive a toggling RAM clock 103, even though the other three banks are not being accessed for read or write operations.
In the case of a single-ported RAM, only one RAM bank, at most, can be accessed at a time; the remaining banks are idle. In the case of a dual-ported RAM, only two RAM banks, at most, are accessed at a time and the remaining banks are idle. However, the idle RAM banks (or RAM EBBs), which are not accessed, still dissipate power, since the RAM clock 103 applied to these idle RAM banks/EBBs is still toggling.